Contact Information：
Professor Yao-Jen Lee
Ph.D. in Electrical Engineering from National Chiao Tung University
Adjunct Research Fellow at Taiwan Semiconductor Research Institute
Primary Email：yjlee1976@gmail.edu.tw
School Email：yjlee1976@nycu.edu.tw
Office： Room 371, Engineering Building 6 (EF-371)
TEL: +886-3-71-2121 ext.58526
Laboratory： Room 453, Engineering Building 6 (EF-453)
TEL: +886-3-71-2121 ext.58520
Introduction of ASD Lab.：
Prof. Yao-Jen Lee worked at Taiwan Semiconductor Research Institute as a research fellow for over 16 years and is currently an adjunct research fellow at TSRI. We have built several advanced device platforms. In 16 years, graduate students from different universities joined our team, and all the research was conducted at the Taiwan Semiconductor Research Institute (TSRI) and NFC of National Yang Ming Chiao Tung University.
1. Research Topics: We work on advanced semiconductor devices, including FinFETs, GAA FETs, Si/Ge CFETs, vertical transistors, metal oxide devices, stacked devices, and high-k materials.
2. Training for Device Fabrication: With the help of experienced students, we have several device fabrication platforms that allow our graduate students to learn and produce advanced devices quickly.
3. Measurement Facilities: Our lab is equipped to perform device measurements over a wide temperature range, from 4K to 150°C.
4. Recent research results:
Fig1. Ge FinFETs Platform： Ge CMOS platform, fabricated on the Ge epitaxial layer on SOI, is used to study Ge properties from the prospectives of finFETs.
Fig2. From 8-Inch Wafers to Wafer Dicing：Transitioning from 8-inch wafers to wafer dicing processes not only reduces device fabrication costs but also enhances the flexibility of our research.
Fig3. Polysilicon Stacked CMOS Platform
Fig4. Polysilicon Stacked CMOS Platform
The polysilicon stacked CMOS platform allows for adjusting the channel count for pFET and nFET using photolithography and etching processes.
- Varying the channel count promotes the current balance.
- Why is there one less channel in pFET? Because the threshold voltage leans towards nFET.
Fig5. Complementary FET (CFET) Platform, Presented at IEDM 2019
- The pFET appears narrower due to the longer etching time.
Fig6. Heterogeneous Integration of Ge/Si CFET Platform.
- In collaboration with AIST Japan, our team utilizes a low-temperature bonding process to bond Ge and Si, forming heterogeneous integrated CFET devices.